Pipeline first, algorithm second

In software SDR, throughput scales with CPU vectorization and cache behavior. In FPGA SDR, throughput is mostly a clocking and dataflow problem. Treat every block as a streaming stage with explicit valid/ready semantics. Typical receive chain:

1. ADC sample ingress
2. Numerically controlled oscillator (NCO) + complex mixer
3. CIC decimator
4. Compensation FIR
5. Matched filter (RRC)
6. Timing recovery and carrier recovery
7. Symbol decisions / soft metrics

Throughput budgeting

Given ADC rate Fs, decimation D, and parallel factor P, the effective internal sample rate per lane is roughly: F_lane = Fs / (D * P) Choose P to trade BRAM/DSP usage against timing margin. A wider parallel datapath often closes timing more reliably than a very high single-lane clock.

Fixed-point discipline

For each stage define:

• Input width
• Growth bits
• Rounding mode
• Saturation behavior

Do not defer scaling decisions. Quantization noise accumulates and can destabilize loops (Costas, Gardner, Mueller and Muller) if SNR margin is already tight.

Verification strategy

• Golden floating-point model in Python/NumPy.
• Bit-accurate fixed-point model.
• HDL simulation with randomized stress vectors.
• Hardware capture/replay loop for post-route validation.

The strongest FPGA SDR teams keep algorithm and implementation co-designed from day one; retrofitting timing closure after full-feature integration is expensive and error-prone.