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Thumbnail of SDR Front-End Reality: IQ Imbalance, DC Offset, and LO Leakage

SDR Front-End Reality: IQ Imbalance, DC Offset, and LO Leakage

March 14, 2026A practical deep dive into non-ideal SDR receiver behavior and how to calibrate around it.

FPGA SDR DSP Pipeline: Deterministic Throughput from ADC to Symbols

March 14, 2026How to architect a high-throughput FPGA receive chain with bounded latency and timing closure in mind.
Thumbnail of CIC + FIR Decimation on FPGA: Alias Control Without Wasting DSP Slices

CIC + FIR Decimation on FPGA: Alias Control Without Wasting DSP Slices

March 14, 2026Design tradeoffs between multiplier-free CIC stages and FIR compensation in practical SDR decimators.

OFDM Receiver Synchronization in SDR: Coarse CFO, Fine CFO, and Timing

March 14, 2026A robust synchronization sequence for OFDM receivers implemented across SDR software and FPGA hardware.

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I occasionally write about design and technology, and share thoughts on the intersection of creativity and engineering.